Random access memory (RAM) is classified into synchronous and asynchronous types. Synchronous RAM latches an address and write data in response to the falling of a chip select signal /CS, for example, accesses the address and executes writing of the latched data.
On the other hand, asynchronous RAM continually operates and after a period an address stays fixed, an access cycle is started, write data is latched in response to the rising of the chip select signal /CS, and writing of the data is executed. Operation of such asynchronous RAM was coordinated with older-generation CPUs, which output the data of a computation result in the second half of a clock cycle. The write method of such asynchronous RAM is called the delayed write method.
Ferroelectric memory (FeRAM) also has synchronous type and pseude-asynchronous type in which address is latched at falling edge of /CS and DATA is not latched thereat. In ferroelectric memory, a memory cell comprises an access gate and a ferroelectric capacitor; data is held through the direction of polarization of the ferroelectric capacitor. When, during readout, a plate line connected to a ferroelectric capacitor is driven to H level, the stored data is read out according to whether there is no change produced by the polarization direction of the ferroelectric capacitor being not changed and the electric charge amount output to bit line is small (for example, data 0), or a change occurs by the polarization direction of the ferroelectric capacitor being changed and and the charge amount is large (for example, data 1).
Further, bit-line termination while the plate line rise of ferroelectric memory is classified into the HiZ method and the BGS (Bit-Line GND Sense) method according to the readout method. In the readout operation of the HiZ method, a bit line is put into a floating state at a precharge level, a word line is selected to cause an access gate to be conducting, and by driving a plate line to H level, the bit line potential is made to change according to the charge amount output by the ferroelectric capacitor in the memory cell. This bit line potential is amplified by a latch amplifier, and brought to either the power supply VDD level or ground GND level. This amplified bit line potential is output as the readout data. Rewriting is performed by driving the plate line to H level or L level while maintaining the bit line potential.
During a write operation in the case of the HiZ method, after the latch amplifier amplifies the bit line potential, a write amplifier drives the bit line potential to the power supply VDD level or GND level according to the write data, the plate line is driven to H level then to L level, and by forming a polarization state in the ferroelectric capacitor, data 0 or 1 is written. If the bit line is at H level and the plate line is at L level, data 1 is written, and if the bit line is at L level and the plate line is at H level, data 0 is written.
In the BGS method, the bit line is fixed at GND level by a input terminal of a QV amplifier, the QV preamplifier amplifies the magnitude of the charge amount output to the bit line when plate line is driven and the charge is converted into a voltage difference at a output terminal of the QV amplifier, and then further amplified to the power supply level or GND level by a latch amplifier. Rewriting is performed by using the write amplifier to drive the bit line and driving the plate line to H level or L level. Write operations are equivalent to rewrite operations.
Ferroelectric memory is disclosed in Japanese laid-open patent publications 2002-197855, H09-121032, 2009-123328, 2001-358312, Japanese registered patents 4031904, 4157528, 4185969, Japanese laid-open patent publications 2002-133857, 2005-293818, 2007-257692, 2008-59676, 2008-234829, and non-patent document, S. Kawashima et al. “Bit-line GND sensing technique for low-voltage operation FeRAM,” IEEE J. SC, Vol. 37, no.5, pp. 592-598, May. 2002.
In the case of the delayed write method, using either the HiZ method or the BGS method, by word line selection, plate line driving, sense amplifier operation and similar, a bit line level is brought to the power supply level or GND level, and after a state in which the plate line has remained at H level has continued, the write data is latched and the write operation is performed. When the active period becomes long and this suspending state is continued for a long time, if the threshold voltage of the access gate of a half-selected cell is low due to manufacturing variances, the node within a half-selected cell connected in common to the selected plate line at H level and with bit line at L level, or the capacitor terminal node within half-selected cells that are cells connected in common to the bit line at the power supply level and with plate line at L level, may become the bit line level due to a leak from the access gate, so that the polarization state of the ferroelectric capacitor is reversed and erroneous writing occurs.